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overview the LC75385NE-R is an electronic volume and tone control ic that can implement volume, balance, fader, bass/treble, loudness, input switching, and input gain control functions with a minimum number of external components. features volume: 81 positions: from 0 db to ?9 db in 1-db steps and . a balance function can be implemented by controlling the left and right volume settings independently. fader: either the rear or front outputs can be attenuated over 16 positions. (16 positions: from 0 db to ? db in 1-db steps, from ? db to ?0 db in 2-db steps, from ?0 to ?0 db in one 10-db step, ?5 db, ?0 db, and .) bass/treble: control over 12 db in 2-db steps in each band. input gain: the input signal can be amplified by from 0 to +18.75 db in 1.25 db steps. input switching: one of four signals can be selected for each of the left and right channels. loudness: taps are output from a 2-db step volume control ladder resistor starting at the ?2-db position. a loudness function can be implemented by attaching external capacitors and resistors. on-chip buffer amplifiers minimize the number of required external components. minimal switching noise when no input signals are present due to fabrication in a silicon gate cmos process that minimizes the noise generated by internal switches. use of zero-cross switching circuits for internal switches minimizes switching noise when signals are present. built-in v dd /2 reference voltage generator circuit all controls can be set from serial input data transferred over a ccb interface. package dimensions unit: mm 3148-qfp44ma 2.8max 0.8 11.6 0.35 10.0 13.2 1.0 1 11 12 22 23 33 34 44 1.0 1.6 0.8 2.5 0.2 0.1 10.0 13.2 1.0 1.0 1.6 0.8 cmos ic 41399rm (ot) no.6143-1/22 sanyo: qfp44ma (qip44ma) [LC75385NE-R] sanyo electric co.,ltd. semiconductor company tokyo office tokyo bldg., 1-10, 1 chome, ueno, taito-ku, tokyo, 110-8534 japan electronic volume and tone control for car stereo systems LC75385NE-R ordering number : en6143 ccb is a trademark of sanyo electric co., ltd. ccb is sanyo? original bus format and all the bus addresses are controlled by sanyo. any and all sanyo products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft? control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. consult with your sanyo representative nearest you before using any sanyo products described or contained herein in such applications. sanyo assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all sanyo products described or contained herein.
no.6143- 2 /22 LC75385NE-R parameter symbol conditions ratings unit min typ max supply voltage v dd v dd 6.0 10.5 v high-level input voltage v ih cl, di, ce 4.0 v dd v low-level input voltage v il cl, di, ce v ss 1.0 v input voltage amplitude v in v ss v dd vp-p input pulse width t ? cl 1 s setup time t setup cl, di, ce 1 s hold time t hold cl, di, ce 1 s operating frequency fopg cl 500 khz allowable operating ranges at ta = 25 c, v ss = 0 v parameter symbol pins conditions ratings unit min typ max [input block] input resistance rin l1 to l4, r1 to r4 30 50 70 k minimum input gain ginmin l1 to l4, r1 to r4 ? 0 +1 db maximum input gain ginmax +16.5 +18.75 +21 db inter-step setting error aterr 0.6 db left/right balance bal 0.5 db [volume block] input resistance rvr lvrin, rvrin, loudness off 113 226 339 k inter-step setting error aterr 0.5 db left/right balance bal 0.5 db [tone control block] inter-step setting error aterr 1.0 db bass control range gbass max. boost/cut 9 12 15 db treble control range gtre max. boost/cut 9 12 15 db left/right balance bal 0.5 db [fader block] input resistance rfed lfin, rfin 25 50 100 k 0 db to ? db 0.5 db inter-step setting error aterr ? db to ?0 db 1 db ?0 db to ?0 db 2 db ?0 db to ?0 db 3 db left/right balance bal 0.5 db electrical characteristics at ta = 25 c, v dd = 9 v, v ss = 0 v parameter symbol conditions ratings unit maximum supply voltage v dd max v dd 11 v maximum input voltage v in max all input pins v ss ?0.3 to v dd + 0.3 v allowable power dissipation pd max ta 85 c, when mounted on a printed circuit board 720 mw operating temperature topr ?0 to +85 c storage temperature tstg ?0 to +125 c specifications absolute maximum ratings at ta = 25 c, v ss = 0 v
no.6143- 3 /22 LC75385NE-R overall characteristics parameter symbol conditions ratings unit min typ max total harmonic distortion thd 1 v in = ?0 dbv, f = 1 khz 0.004 % thd 2 v in = ?0 dbv, f = 10 khz 0.006 % inter-input crosstalk ct v in = 1 vrms, f = 1 khz 80 88 db left/right channel crosstalk ct v in = 1 vrms, f = 1 khz 80 88 db maximum attenuation v o min 1 v in = 1 vrms, f = 1 khz 80 88 db v o min 2 v in = 1 vrms, f = 1 khz, inmute, with the fader set to 90 95 db output noise voltage v n 1 all controls flat, with the ihf-a filter 5 10 v v n 2 all controls flat, with a 20 hz to 20 khz bandpass filter 7 15 v current drain i dd 33 40 ma high-level input current i ih cl, di, ce, v in = 9 v 10 a low-level input current i il cl, di, ce, v in = 0 v ?0 a maximum input voltage v cl thd = 1 %, r l = 10 k , all controls flat, fin = 1 khz 2.5 2.9 vrms pin arrangement 1 rselo 2 rvrin 3 rct 4 rcom 5 rvrout 6 rtin 7 rf1c1 8 rf1c2 9 rf1c3 10 rf3c1 11 12 rfin 13 rfout 14 rrout 15 tim 16 av ss 17 ce 18 di 19 cl 20 dv ss 21 lrout 22 23 lfin 24 ltout 25 lf3c1 26 lf1c3 27 lf1c2 28 lf1c1 29 ltin 30 lvrout 31 lcom 32 lct 33 34 lselo 35 l4 36 l3 37 l2 38 l1 39 v dd 40 vref 41 r1 42 r2 43 r3 44 r4 lvrin lfout rtout LC75385NE-R a12263 top view printed circuit board size: 76.1 114.3 1.6 mm printed circuit board material: fiberglass/epoxy ambient temperature, ta ( c) allowable power dissipation, pdmax (w) mounted on the stipulated printed circuit board independent device
no.6143- 4 /22 LC75385NE-R equivalent circuit and sample application circuit diagram multiplexer multiplexer
no.6143- 5 /22 LC75385NE-R pin functions pin no. pin function notes ?single end inputs 38 37 36 35 41 42 43 44 l1 l2 l3 l4 r1 r2 r3 r4 ?input selector outputs 34 1 lsel0 rsel0 ?inputs for the 2-db step volume control ?these inputs must be driven from low-impedance circuits. 33 2 lvrin rvrin ? loudness function pins. connect the high-band compensation rc circuits between the lct (rct) and the lvrin (rvrin) pins and connect the low-band compensation rc circuits between the lct (rct) and vref. 32 3 lct rct ?2-db step volume control outputs ?to reduce switching noise, each of these pins should be connected to vref through a capacitor. 31 4 lcom rcom ?output from the 1-db step volume control 30 5 lvrout rvrout ?tone control circuit inputs 29 6 ltin rtin continued on next page.
no.6143- 6 /22 LC75385NE-R continued from preceding page. pin no. pin function equivalent circuit ?tone control circuit high band filter capacitor connections the high band compensation capacitors must be connected between lf3c1 (rf3c1) and vref. 39 10 lf3c1 rf3c1 ?tone control circuit outputs 24 11 ltout rtout ?fader block inputs ?these inputs must be driven from low-impedance circuits. 23 12 lfin rfin ?fader block outputs. the front and rear outputs can be attenuated independently. the attenuation is the same in the left and right channels. 22 21 13 14 lfout lrout rfout rrout ?v dd /2 voltage generator block. a capacitor with a value of about 10 f must be inserted between vref and av ss (v ss ) to reduce power supply ripple. 40 vref ?power supply 39 v dd ?tone control circuit low band filter capacitor connections the low band compensation capacitors must be connected between the following pins: lf1c1 (rf1c1) and lf1c2 (rf1c2) lf1c2 (rf1c2) and lf1c3 (rf1c3) 28 27 26 7 8 9 lf1c1 lf1c2 lf1c3 rf1c1 rf1c2 rf1c3 ?logic system ground 20 dv ss ?analog system ground 16 av ss continued on next page.
no.6143- 7 /22 LC75385NE-R continued from preceding page. pin no. pin function equivalent circuit ?serial data and clock inputs used for device control 19 18 cl di ?used for the zero cross circuit no-signal timer function. if a zero cross signal does not occur between the point when data is loaded and the point when the timer times out, the data will be stored forcibly when the timer times out. 15 tim 17 ce ?chip enable input. data is written to the internal latch when this pin goes from high to low. the analog switches then operate. data transfers are enabled when this pin is high. internal equivalent circuits selector block equivalent circuit total resistance: 50 k the right channel is identical. unit (resistance: )
no.6143- 8 /22 LC75385NE-R 2-db step volume control block equivalent circuit ? the total resistance above the tap is 195 k to the left channel 1-db step block ? the total resistance below the tap is 30.847 k switch used for initial setup the right channel is identical. unit (resistance: )
no.6143- 9 /22 LC75385NE-R 1-db step volume control block equivalent circuit unit: (resistance : ) total resistance: 50 k the right channel is identical. tone control block equivalent circuit from the left channel 2-db volume control block switch used for initial setup switch used for initial setup unit: (resistance : )
no.6143- 10 /22 LC75385NE-R fader volume control block equivalent circuit when fader is set to 1, s2 and s3 will be turned on. when fader is set to 0, s1 and s4 will be turned on. unit: (resistance : ) total resistance: 50 k if data that sets the main volume control 1-db step circuit to is sent to the device, switches s1 and s2 will be opened (off) and switches s3 and s4 will be closed (on).
control system timing and data format the LC75385NE-R is controlled by applying the stipulated data to the cl, di, and ce pins. the data consists of a total of 52 bits, of which 8 bits are the device address and 44 bits are the actual control data. address code (b0 to a3) the LC75385NE-R has an 8-bit address code, and can be used along with other ics that support the sanyo ccb serial bus. no.6143- 11 /22 LC75385NE-R address code b0 b1 b2 b3 a0 a1 a2 a3 1 0 0 0 0 0 0 1 (lsb) (81hex) control code allocation d0 d1 d2 0 0 0 l1 (r1) 1 0 0 l2 (r2) 0 1 0 l3 (r3) 1 1 0 l4 (r4) 0 1 1 1 1 1 input switching control ic test values. these values must not be used during normal operation. d3 ic test bit. this bit must be set to 0 during normal operation. 1 s t dest
no.6143- 12 /22 LC75385NE-R d4 d5 d6 d7 0 0 0 0 0 db 1 0 0 0 +1.25 db 0 1 0 0 +2.50 db 1 1 0 0 +3.75 db 0 0 1 0 +5.00 db 1 0 1 0 +6.25 db 0 1 1 0 +7.50 db 1 1 1 0 +8.75 db 0 0 0 1 +10.0 db 1 0 0 1 +11.25 db 0 1 0 1 +12.5 db 1 1 0 1 +13.75 db 0 0 1 1 +15.0 db 1 0 1 1 +16.25 db 0 1 1 1 +17.5 db 1 1 1 1 +18.75 db input gain control
no.6143- 13 /22 LC75385NE-R d8 d9 d10 d11 d12 d13 d14 d15 1 db step 0 0 db 1 ? db 2 db step 0 0 0 0 0 0 0 0 db 1 0 0 0 0 0 0 ? db 0 1 0 0 0 0 0 ? db 1 1 0 0 0 0 0 ? db 0 0 1 0 0 0 0 ? db 1 0 1 0 0 0 0 ?0 db 0 1 1 0 0 0 0 ?2 db 1 1 1 0 0 0 0 ?4 db 0 0 0 1 0 0 0 ?6 db 1 0 0 1 0 0 0 ?8 db 0 1 0 1 0 0 0 ?0 db 1 1 0 1 0 0 0 ?2 db 0 0 1 1 0 0 0 ?4 db 1 0 1 1 0 0 0 ?6 db 0 1 1 1 0 0 0 ?8 db 1 1 1 1 0 0 0 ?0 db 0 0 0 0 1 0 0 ?2 db 1 0 0 0 1 0 0 ?4 db 0 1 0 0 1 0 0 ?6 db 1 1 0 0 1 0 0 ?8 db 0 0 1 0 1 0 0 ?0 db 1 0 1 0 1 0 0 ?2 db 0 1 1 0 1 0 0 ?4 db 1 1 1 0 1 0 0 ?6 db 0 0 0 1 1 0 0 ?8 db 1 0 0 1 1 0 0 ?0 db 0 1 0 1 1 0 0 ?2 db 1 1 0 1 1 0 0 ?4 db 0 0 1 1 1 0 0 ?6 db 1 0 1 1 1 0 0 ?8 db 0 1 1 1 1 0 0 ?0 db 1 1 1 1 1 0 0 ?2 db 0 0 0 0 0 1 0 ?4 db 1 0 0 0 0 1 0 ?6 db 0 1 0 0 0 1 0 ?8 db 1 1 0 0 0 1 0 ?0 db 0 0 1 0 0 1 0 ?2 db 1 0 1 0 0 1 0 ?4 db 0 1 1 0 0 1 0 ?6 db 1 1 1 0 0 1 0 ?8 db mute 1 1 1 1 1 1 0 0 1 1 1 1 1 0 inmute volume control
no.6143- 14 /22 LC75385NE-R d16 d17 d18 d19 bass d24 d25 d26 d27 treble 0 1 1 0 +12 db 1 0 1 0 +10 db 0 0 1 0 +8 db 1 1 0 0 +6 db 0 1 0 0 +4 db 1 0 0 0 +2 db 0 0 0 0 0 db 1 0 0 1 ? db 0 1 0 1 ? db 1 1 0 1 ? db 0 0 1 1 ? db 1 0 1 1 ?0 db 0 1 1 1 ?2 db tone control d20 d21 d22 d23 0 0 0 0 these bits must be set to 0 fader volume control d28 d29 d30 d31 0 0 0 0 0 db 1 0 0 0 ? db 0 1 0 0 ? db 1 1 0 0 ? db 0 0 1 0 ? db 1 0 1 0 ? db 0 1 1 0 ?0 db 1 1 1 0 ?2 db 0 0 0 1 ?4 db 1 0 0 1 ?6 db 0 1 0 1 ?8 db 1 1 0 1 ?0 db 0 0 1 1 ?0 db 1 0 1 1 ?5 db 0 1 1 1 ?0 db 1 1 1 1 channel selection control d32 d33 0 0 left and right together. this is the mode set up initially 1 0 rch 0 1 lch 1 1 left and right together fader rear/front control d34 0 rear 1 front
no.6143- 15 /22 LC75385NE-R loudness control d35 0 off 1 on zero cross control d36 d37 0 0 data is written when a zero cross is detected 1 1 the zero cross detection operation is disabled and data is written on the falling edge of the ce signal d38 d39 d40 d41 0 0 0 0 selector 1 0 0 0 volume 0 1 0 0 tone 1 1 0 0 feder zero cross signal detection block control test mode control d42 d43 0 0 these ic test mode control bits must be set to 0
usage notes data transmission after power is first applied ? when power is first applied, the state of the internal analog switches will be undefined. applications that use this ic must include external circuits to provide muting until control data has been transferred to the ic. ? after power is first applied, applications should send initial setup data to stabilize the bias levels in each of the ic circuit blocks in a short time. 1. the time between initial setup mode and the first actual data settings ?applications should send the initial setup data as soon as v dd rises above 6 v. ?after the lcom and rcom pins have stabilized at the vref level, applications should send the first data settings. 2. procedure for setting up initial setup mode ? when d32 and d33 are set to 00, the ic? internal initial setup switch is turned on and the ic goes to quick charge mode. at this time the other data (d0 to d31 and d34 to d43) will also be set up for the left and right channels at the same time. this means that applications can set up the states of the various blocks at the same time as specifying initial setup mode. 3. procedure for clearing initial setup mode ? initial setup mode is cleared by setting d32 and d33 to any value other than 00. in other words, any normal left or right channel specification will turn the internal initial setup switch off and clear quick charge mode. no.6143- 16 /22 LC75385NE-R the time required for the capacitors connected to the lcom and rcom pins to be charged to the vref level these operations clear initial setup mode the 1/2 v dd level v dd = 9 v (typ) v dd = 6 v initial setup mode first data for the left channel first data for the right channel data
zero cross switching circuit operating principles the LC75385NE-R includes a function for switching the place where the zero cross comparator operates and thus allows applications to select the optimal detection location for the block for which the control data is updated. basically, switching noise will be minimized if the signal immediately following the block for which the control data is updated is input to the zero cross comparator. thus the detection location must be changed for each data update operation. another issue is the point that if the signal amplitude is lower than the detection sensitivity (a few mv rms) of the zero cross comparator (for example if the volume is set to a low level), the switching noise can be minimized further by selecting a point before the volume control block, namely the selector block output, as the zero cross detection point than by simply waiting for the data write to occur due to the overflow of the zero cross timer. for example, if the volume block input is 1 v rms, and the volume is set to ?0 db or lower, the output will be under 10 mv rms. in this case, detecting at the selector output block will result in lower switching noise. no.6143- 17 /22 LC75385NE-R zero cross switching control procedure the zero cross switching control procedure consists of first setting the zero cross detection mode with the zero cross control bits (d36 and d37 = 0) and then, after specifying the detection block (with bits d38, d39, d40, and d41), sending the control data. since these control bits are latched first immediately after the data is sent, i.e. on the falling edge of the ce signal, it is possible to both set the ic mode as well as specify zero cross switching operation in a single data transfer, even when updating the volume and other data. the following presents an example of the control operation when updating the volume block data. d36 zero cross detection mode specification volume block setting d37 d38 d39 d40 d41 0 0 1 0 0 0 zero cross timer setting when the input signal has a level lower than the sensitivity of the zero cross comparator, or consists only of extremely low frequencies, the zero cross detection circuit will remain in the state in which it cannot detect a zero cross and the data will not be latched during that period. the zero cross timer specifies a time after which the data will be latched forcibly in states where a zero crossing cannot be detected. the time is determined by the lowest frequency for which a zero cross can be detected reliably. for example, if the timer is set to 25 ms: t = 0.69 cr if c is taken to be 0.033 f, then r will be: r = 25 10 -3 1.1 m 0.69 0.033 10 -6 selector volume tone fader switch zero cross comparator zero cross detection circuit
notes on serial data transfer ? the cl, di, and ce pin signal lines must be covered (and thus shielded) by the ground pattern or formed from shielded cable to prevent the high-frequency digital signals on those lines from entering the analog system. ? the LC75385NE-R data format consists of 8 bits of address and 44 bits of data. when the data is sent in units of 8 bits each (i.e. 48 bits are actually sent), use the data transfer technique shown in figure 1. LC75385NE-R data reception in 8-bit units no.6143- 18 /22 LC75385NE-R dummy data ? during ccb transfers, this ic detects address matches on the rising edge of the ce signal. therefore, applications must set the cl signal low and then set it high at this time. input switching control test mode control
no.6143- 19 /22 LC75385NE-R fader block main volume step characteristics attenuation ?db step ?db input gain block main volume block graphic equalizer block gain step characteristics step ?db output level ?db fader volume step characteristics step ?db fader volume attenuation ?db thd ?frequency characteristics total harmonic distortion, thd ?% frequency, f ?hz fader block input gain block main volume block graphic equalizer block fader block input gain block main volume block graphic equalizer block fader block input gain block main volume block graphic equalizer block 80-khz low pass weighting
no.6143- 20 /22 LC75385NE-R loudness characteristics level ?db frequency, f ?hz output level characteristics flat overall input = l1, output = lfout settings: the 0 db to ?4 db positions (in ? db steps) flat overall input = l1, output = lfout settings: the 0 db to ?4 db positions (in ? db steps) output level ?dbv frequency, f ?hz
no.6143- 21 /22 LC75385NE-R fader block thd ?input level characteristics input gain block main volume block graphic equalizer block thd ?supply voltage characteristics supply voltage ?v total harmonic distortion, thd ?% bass control characteristics frequency, f ?hz level ?db treble control characteristics frequency, f ?hz fader block input gain block main volume block graphic equalizer block total harmonic distortion, thd ?% input level, v in ?dbv 80-khz low pass weighting with vr set to the 0 db position 80-khz low pass weighting level ?db input = l1, output = lfout, 10000 pf input = l1, output = lfout
this catalog provides information as of april, 1999. specifications and information herein are subject to change without notice. specifications of any and all sanyo products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer? products or equipment. to verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer? products or equipment. sanyo electric co., ltd. strives to supply high-quality high-reliability products. however, any and all semiconductor products fail with some probability. it is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. when designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. in the event that any or all sanyo products (including technical data, services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of sanyo electric co., ltd. any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. when designing equipment, refer to the ?elivery specification for the sanyo product that you intend to use. information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. sanyo believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. ps no.6143- 22 /22 LC75385NE-R

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